Integrated circuits are formed on wafers by well-known processes and materials. These processes typically include the deposition of thin film layers by sputtering, metal-organic decomposition, chemical vapor deposition, plasma vapor deposition, and other techniques. These layers are processed by a variety of well-known etching technologies and subsequent deposition steps to provide a completed integrated circuit.
A crucial component of integrated circuits is the wiring or metallization layer that interconnects the individual circuits. Conventional metal deposition techniques include physical vapor deposition (e.g., sputtering and evaporation) and chemical vapor deposition techniques. Integrated circuit manufacturers have also developed electrolytic and electroless plating techniques to deposit primary conductor films on semiconductor substrates.
Wiring layers traditionally contained aluminum and a plurality of other metal layers that are compatible with aluminum. In 1997, IBM introduced technology that facilitated a transition from aluminum to copper wiring layers. This technology demanded corresponding changes in process architecture towards damascene and dual damascene architecture, as well as new process technologies.
Copper damascene and dual damascene circuits are produced by initially forming trenches and other embedded features in a wafer, as needed for circuit architecture. These trenches and embedded features are formed by conventional photolithographic processes in a nonconductive substrate, such as a silicon oxide. A barrier layer, for example, of silicon nitride or tantalum, is deposited next. An initial seed or strike layer, (e.g., a copper or ruthenium layer having a thickness of about 5 nanometers (nm) to 200 nm) is then deposited by a conventional physical or vapor deposition technique. The seed layer is used as a base layer to conduct current for electroplating thicker films. Thinner seed layers are preferred to reduce overhang and closure of very small features by metal from the seed layer. The seed layer functions as the initial cathode of an electroplating cell. Electrical contacts to the wafer are normally made at its edge.
Generally, in electroplating processes, the thickness profile of the deposited metal is controlled to be as uniform as possible. This uniform profile is advantageous in subsequent etchback or polish removal steps, as well as in uniform void-free filling of the trench structures. Prior art electroplating techniques are susceptible to thickness irregularities. Factors contributing to these irregularities include the size and shape of the electroplating cell, electrolyte depletion effects, hot edge effects, and the terminal effect.
The introduction of damascene metallization for copper interconnects led to the development and modification of processes. The implementation of new process flows resulted in the formation of device-killing defects, as well as nuisance defects, which interfere with the ability to identify accurately the device-killing defects. In copper damascene metallization, defects generally arise during the three main process sequences: deposition of barrier and seed layers; electrofill operations, including pre- and post-anneal; and chemical mechanical polishing (CMP). Critical post-plating in-film killer defects in electroplated copper layers include pits, craters, and voids, which typically form during the electroplating process or during the post-plate anneal steps. Another type of defects include protrusions, surface debris and embedded particles.
Electroless plating (or electroless deposition) of copper and other metals has received increasing interest in recent years. This interest is due in part because of the relatively low cost of electroless processes compared to other (e.g., vacuum) deposition techniques, and because of generally surface-controlled, selective, conformal deposition of electroless processes. Electroless deposition has a number of potential applications, such as repair of marginal seed layers for copper damascene electroplating, creation of seed layers and barrier layers directly on dielectric material, and selective deposition of barrier and electromigration capping layers onto damascene metal (e.g., cobalt and cobalt alloys on copper). Conventional electroless metal deposition is conducted in a system containing one or multiple open baths containing plating solution. In a typical operation, a wafer holder immerses a substrate wafer face down in the plating solution during plating operations.
Wafer immersion into an electroless or electrolytic plating bath generally comprises no more than five hundred milliseconds of a plating process, which typically lasts a few tens of seconds up to a few minutes. Yet, the defects formed as a result of entry conditions often critically affect yield (the number of chips that function in a full wafer). One of the reasons defects form as a result of wafer immersion into a plating bath is because of air trapped during entry. Air bubbles trapped on the plating surface of a wafer cause numerous problems. Bubbles shield a region of the plating surface of a wafer from exposure to electrolyte, and thus produce a region where plating does not occur. The resulting plating defect can manifest itself as a region of no plating or of reduced thickness, depending on the time at which the bubble became entrapped on the wafer and the length of time that it stayed entrapped there. In an inverted (face down) configuration, buoyancy forces tend to pull bubbles upwards and onto the wafer's active planar surface. Bubbles are difficult to remove from the wafer surface because the plating cell has no intrinsic mechanism for driving the bubbles around the wafer edges, the only path off the wafer surface. For example, FIG. 1 depicts schematically a representative plating system 102 of the prior art in which bubbles 104 and air 105 are trapped on wafer surface 106 of a semiconductor wafer 108 after its immersion into a plating bath 110. Typically, a wafer is rotated about an axis that passes through its center and is perpendicular to its planar plating surface. This helps to dislodge bubbles through centrifugal force, but many of the smaller bubbles are tenacious in their attachment to the wafer. Another problem associated with immersion of a horizontally oriented wafer is multiple wetting fronts. When a wafer is immersed in this way, the electrolyte contacts the wafer at more than one point, creating multiple wetting fronts as the wafer is submerged in the electrolyte. Where individual wetting fronts converge, bubbles may be trapped. Also, defects in the finished plating layer can be propagated from microscopic unwetted regions formed along convergence lines of multiple wetting fronts.
Various methods have been suggested for avoiding problems commonly encountered in deposition of metal, particularly electroplating of copper, in integrated circuit fabrication. For example, U.S. Pat. No. 6,551,487, issued Apr. 22, 2003, to Reid et al., which is hereby incorporated by reference, teaches a method and an apparatus for controlling the angle and speed of wafer immersion into a plating solution to reduce multiple wetting fronts and air bubble formation on the substrate surface and, thereby, to reduce electroplating defects. U.S. Pat. No. 6,551,487 teaches that an angle of about 5 degrees to horizontal and a slow immersion speed of about 12 millimeter (mm) per second is effective for minimizing bubble formation. Co-owned and co-pending United States Patent Application Publication Number 2008/0149489, published Jun. 26, 2008, by Varadarajan et al., having the title “Multistep Immersion of Wafer into Liquid Bath”, which is hereby incorporated by reference, teaches a short pause time during the wafer immersion process to avoid bubble formation on the wafer surface.
As the industry transitions to design nodes of 90 nm and smaller, proper wetting of embedded features (i.e., the displacement of gas from the spaces within features and its replacement with plating solution) favors a relatively high shear force on the wafer. A high shear force, however, is inconsistent with the technique of using a relatively slow wafer immersion speed to minimize bubble formation and resulting defects. Also, even with angled immersion of a wafer into a plating bath, bubbles still have a tendency to form and to be trapped near the outer edge of the wafer surface where a wafer holder encompasses the wafer edge. For example, FIG. 2 depicts schematically a plating system 122 of the prior art in which bubbles 124 are trapped at the outer edge region 126 of wafer surface 128 by the outer lower edge 130 of wafer holder 132. When the leading lower edge 130 of a wafer holder 132 and the leading outer edge region 126 of wafer surface 128 pierce the liquid surface 134 of a plating bath 136, a turbulent zone is created and small air bubbles contact the leading edge 124 of the wafer. This can lead to an on-wafer defect referred to as a C-line defect. A C-line defect shows up as an arc-shaped defect pattern at the very edge of the wafer. The C-line itself often consists of pits or comets which are killer-type defects. Further, a volume of air 140 is often trapped at the trailing lower edge 142 of wafer holder 132. This trapped air volume 140 arises in the void space created as a result of the trailing lower edge 142 being lower than the plane of wafer surface 128 near trailing lower edge 142. The design of wafer holder geometry reduces, but does not eliminate, this trapped air volume at trailing edge 142 of the wafer holder. Also, excessive turbulence is often generated at trailing edge 142 when a wafer holder reaches its plating position in a plating bath and tilts back to a 0° angle (usually horizontal) parallel to the plane of the anode 144. Bubbles thereby created deflect off the plating chamber wall 146 and contact wafer surface 128, rather than being expelled from the plating chamber.
U.S. Pat. No. 5,653,860, issued Aug. 5, 1997, to Nicholls et al., teaches using mechanical vibrations caused by an ultrasonic transducer to remove air bubbles from the surface of an article during electroplating. U.S. Pat. No. 6,797,135, issued Sep. 28, 2004, to Kim et al., teaches using sonic energy to generate minute bubbles from dissolved gases, which bubbles clean an object and thereby enhance electroplating. U.S. Pat. No. 6,224,713, issued May 1, 2001, to Hembree et al., teaches an ultrasonic etching technique in which ultrasonic waves create turbulence and cavities that mix an etching solution at a microscopic level, enhance concentration uniformity, and dislodge bubbles from the surface to be etched. U.S. Pat. No. 6,428,661, issued Aug. 6, 2002, to Hongo, teaches an ultrasonic oscillating member that prevents bubbles generated during electroplating from adhering to a semiconductor wafer. U.S. Pat. No. 6,626,196, issued Sep. 30, 2003, to Downes, Jr. et al., teaches ultrasonic degassing of electroplating liquid and ultrasonic degassing of high aspect ratio features prior to wet chemical processing.